High-speed digital communication typically requires transmitters and receivers to be synchronized. Such synchronization can be accomplished using a shared clock signal, or the receiver can derive a clock signal from received data. In either case, the clock signal oscillates between high and low states to create carefully timed signal edges that are used to coordinate the transmitter and receiver.
It is not necessary to coordinate the transmitter and receiver when no information is being conveyed between them, and clock signals consume considerable power. Clock circuitry is therefore disabled, or placed in an “idle” state, when not in use. Clock signals require time to stabilize after transitioning from the idle state. Circuits that rely on clock signals in such systems are therefore designed to ignore early clock edges until the clock signal has had an opportunity to stabilize. In high-speed, low-power systems this wait time has an unacceptable impact on performance and system complexity.